DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 516

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–14
Figure 5–12. Standard PCS Custom 20-Bit PMA-PCS Interface Width
Notes to
(1) The maximum data rate specification shown in
(2) The byte ordering block is available only if you select the word alignment pattern length of 20 bits.
Stratix V Device Handbook Volume 3: Transceivers
Number of Bonded Channels
Word Aligner (Pattern Length)
Tx Bit Slip
Rate Match FIFO
8B/10B Encoder/Decoder
Byte Serializer/Deserializer
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Data Rate (Gbps) (1)
other speed grades, refer to the
Figure
5–12:
f
Figure 5–12
interface width. The maximum frequencies shown in
devices.
For more information about the maximum data rate for a certain speed grade, refer to
the
DC and Switching Characteristics for Stratix V Devices
DC and Switching Characteristics for Stratix V Devices
shows the available options for the standard PCS custom 20-bit PMA-PCS
Figure 5–12
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
20-Bit
212.5
4.25
50 -
1.0-
Disabled
Optional
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Disabled
40-Bit
212.5
25 -
Enabled
Synchronization State Machine,
1.0-
8.5
Manual Alignment, Automatic
Enabled (2)
chapter.
40-Bit
162.5
Standard PCS Custom and Low Latency Configurations
25 -
or Bit Slip
Disabled
Up to ×5
Figure 5–12
chapter.
Disabled
May 2011 Altera Corporation
Disabled
16-Bit
212.5
are for the fastest
50 -
1.0-
3.4
Optional
Enabled
Enabled
Disabled
212.5
32-Bit
1.0-
25 -
8.5