DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 359

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 12: Power Management in Stratix V Devices
Stratix V External Power Supply Requirements
Stratix V External Power Supply Requirements
Temperature Sensing Diode
May 2011 Altera Corporation
f
f
■
If a phase-locked loop (PLL) is instantiated in the design, user may assert the areset
pin high to keep the PLL in low-power mode.
Table 12–1
considerations can add to the permutations to give you flexibility in designing your
system.
Table 12–1. Programmable Power Capabilities for Stratix V Devices
This section describes the different external power supplies required to power
Stratix V devices. You can supply some of the power supply pins with the same
external power supply, provided they have the same voltage level requirements.
For more information about power supply pin connection guidelines and power
regulator sharing, refer to the
For each Altera-recommended power supply’s operating conditions, refer to the
and Switching Characteristics
The Stratix V TSD uses the characteristics of a PN junction diode to determine die
temperature. Knowing the junction temperature is crucial for thermal management.
Historically, junction temperature is calculated using ambient or case temperature,
junction-to-ambient (ja) or junction to-case (jc) thermal resistance, and device power
consumption. Stratix V devices can either monitor its die temperature with the
internal TSD with built-in ADC circuitry or the external TSD with an external
temperature sensor. This allows you to control the air flow to the device.
LAB
Routing
Memory Blocks
DSP Blocks
Global Clock Networks
Note to
(1) Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By
DSP blocks
default, unused DSP blocks and memory blocks are set to low-power mode.
Table
lists the available Stratix V programmable power capabilities. Speed grade
12–1:
Feature
chapter.
Stratix V Device Family Pin Connection
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Yes
Yes
Fixed setting
Fixed setting
No
Programmable Power Technology
(1)
(1)
Guidelines.
DC
12–3