DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 287

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Configuration Schemes
Configuration Schemes
Table 9–4. Configuration Schemes for Stratix V Devices (Part 1 of 2)
May 2011 Altera Corporation
Configuration Scheme
FPP ×8
FPP ×16
FPP ×32
PS
AS (×1, ×4)
MSEL Pin Settings
(3)
1
The following sections describe configuration schemes for Stratix V devices.
Select the configuration scheme by driving the Stratix V device MSEL pins either high
or low (refer to
supply. Altera recommends hardwiring the MSEL pins to V
POR and during reconfiguration, the MSEL pins must be at the LVTTL V
levels to be considered logic low and logic high, respectively.
To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL pins to V
the MSEL pins with a microprocessor or another device.
Table 9–4
lists the configuration schemes for Stratix V devices.
Decompression
Optional
Optional
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Feature
Enabled
Enabled
Enabled
CCPGM
Table
(1)
(1)
9–4). The MSEL input buffers are powered by the V
or GND without pull-up or pull-down resistors. Do not drive
Optional
Optional
Optional
Optional
Optional
Security
Disabled
Disabled
Disabled
Feature
Enabled
Enabled
Enabled
Design
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(1)
(1)
(1)
(1)
(1)
Voltage Standard
Configuration
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
1.8/2.5/3.0
(V)
3.0
(2)
CCPGM
POR Delay
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
(5)
or GND. During
CCPGM
IL
MSEL[4..0]
and V
10100
11000
10101
11001
10110
11010
00000
00100
00001
00101
00010
00110
01000
01100
01001
01101
01010
01110
10000
10001
10010
10011
power
IH
9–7