DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 465

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Interlaken
Figure 4–7. Interlaken Configuration
May 2011 Altera Corporation
Transceiver Datapath Configuration
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
PCS-PMA Interface Width
Gear Box and Bit Slip
Block Synchronizer
Disparity Generator/Checker
Scrambler, Descrambler (Mode)
64B/66B Encoder/Decoder
BER Monitor
Frame Generator, Synchronizer
TX FIFO, RX FIFO (Mode)
FPGA Fabric-to-Transceiver
Interface Width
CRC32 Generator, Checker
FPGA Fabric-to-Transceiver
Interface Frequency
Figure 4–7
configuration. Blocks shown as “Disabled” are not used, but incur latency. Blocks
shown as “Bypassed” are not used and do not incur any latency.
shows the transceiver blocks and settings enabled in an Interlaken
3.125, 5, 6.25, 6.375, 10.3125 Gbps
(Frame Synchronous Mode)
78.125 to 257.8125 MHz
Interlaken PHY IP
1-bit Control Data
(Generic Mode)
64-bit Data
Bypassed
Bypassed
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
40-Bit
×1
Stratix V Device Handbook Volume 3: Transceivers
4–9