DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 407

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
10G PCS Architecture
May 2011 Altera Corporation
1
Block Synchronizer
The block synchronizer
specification and the 10GBASE-R protocol specification as described in IEEE
802.3-2008 clause-49.
The block synchronizer determines the block boundary of a 66-bit word in the case of
10GBASE-R or a 67-bit word in the case of Interlaken. The incoming data stream is
slipped one bit at a time until a valid synchronization header (bits 65 and 66) is
detected in the received data stream. After the predefined number of synchronization
headers (as required by the protocol specification) is detected, it asserts the status
signal to other receiver PCS blocks down the receiver datapath and to the FPGA
fabric.
Figure 1–31. Block Synchronizer
Disparity Checker
The design of the disparity checker is based on the Interlaken protocol specifications.
After word synchronization is achieved, the disparity checker monitors the status of
the 67th bit of the incoming word and determines whether or not to invert bits [63:0]
of the received word.
The disparity checker is only used in the Interlaken configuration.
Table 1–14
Table 1–14. Interpretation of the MSB in the 67-Bit Payload for Stratix V Devices
Descrambler
The descrambler descrambles received data per the protocol specifications supported
by the 10G PCS.
The descrambler operates in two modes:
■
■
MSB
Frame synchronous
Self synchronous
0
1
Data Output to Descrambler
Checker in Interlaken Mode
Data Output to Disparity
Bits [63:0] are not inverted; the receiver may process this word without modification
Bits [63:0] are inverted; the receiver must invert the word to achieve the original word
before processing it
in 10GBASE-R Mode
interprets the MSB in the 67-bit word.
(Figure
1–31) is designed towards both the Interlaken protocol
Block Synchronizer
Interpretation
Stratix V Device Handbook Volume 3: Transceivers
66-Bit Data from RX Gear Box
in 10GBASE-R Mode
67-Bit Data from RX Gear Box
in Interlaken Mode
1–35