DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 288

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–8
Table 9–4. Configuration Schemes for Stratix V Devices (Part 2 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Configuration Scheme
JTAG-based configuration
Notes to
(1) You can select to enable or disable this feature.
(2) The configuration voltage standard applied to the V
(3) The AS configuration scheme supports the remote system upgrade feature. For more information about the remote system upgrade feature,
(4) JTAG-based configuration takes precedence over other configuration schemes. This means the MSEL pin settings are ignored. JTAG-based
(5) For POR delay specification, refer to
(6) Do not leave the MSEL pins floating. Connect them to V
refer to
configuration does not support the design security or decompression features.
If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND.
Table
Raw Binary File Size
“Remote System Upgrades” on page
9–4:
For the POR delay specification, refer to
Table 9–5
Table 9–5. Uncompressed .rbf Sizes for Stratix V Devices
Note to
(1) These values are preliminary.
(4)
Stratix V GX
Stratix V GT
Stratix V GS
Stratix V E
Table
Family
lists the uncompressed raw binary file (.rbf) sizes for Stratix V devices.
Decompression
“POR Delay Specification” on page
9–5:
Disabled
Feature
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9–44.
CCPGM
CCPGM
power supply that powers all the configuration pins during configuration.
or GND. This pin supports the non-JTAG configuration scheme used in production.
5SGXA3
5SGXA4
5SGXA5
5SGXA7
5SGXA9
5SGXAB
5SGXB5
5SGXB6
5SGTC5
5SGTC7
5SGSD2
5SGSD3
5SGSD4
5SGSD5
5SGSD6
5SGSD8
Device
5SEEB
5SEE9
Security
Disabled
Feature
Design
9–2.
“POR Delay Specification” on page
Voltage Standard
Configuration
(V)
—
(2)
Configuration .rbf Size (bits)
(Note 1)
139,255,840
139,255,840
266,599,584
266,599,584
387,394,048
387,394,048
266,798,896
266,798,896
266,035,472
266,035,472
209,935,224
209,935,224
266,798,896
266,798,896
387,394,048
387,394,048
93,080,448
93,080,448
POR Delay
—
(5)
May 2011 Altera Corporation
Configuration Schemes
MSEL[4..0]
(6)
9–2.