DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 112

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–18
Figure 2–16. Same-Port Read-During-Write—New Data Mode
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
q_a (asynch)
address
byteena
data_a
clk_a
wren
rden
Figure 2–15
Figure 2–15. Read-During-Write Data Flow for Stratix V Devices
Same-Port Read-During-Write Mode
This mode applies to either a single-port RAM or the same port of a true dual-port
RAM. In same-port read-during-write mode, two output choices are available—new
data mode (or flow-through) or don’t care mode. If the MLAB is selected in same-port
read-during-write mode, only the don’t care mode is available. In new data mode, the
new data is available on the rising edge of the same clock cycle on which it was
written. In don’t care mode, the RAM outputs “don’t care” values for a
read-during-write operation.
Figure 2–16
behavior in new data mode.
shows the difference between the two types.
shows sample functional waveforms of same-port read-during-write
A123
Port A
data in
Port A
data out
A123
B456
0A
B456
C789
C789
11
DDDD
DDDD
Chapter 2: Memory Blocks in Stratix V Devices
0B
EEEE
Port B
data in
Port B
data out
EEEE
FFFF
May 2011 Altera Corporation
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Design Considerations
Mixed-port
data flow
Same-port
data flow