DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 400

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–28
Stratix V Device Handbook Volume 3: Transceivers
Byte Ordering Block in Single-Width Modes
In custom single-width configuration, you can program a custom byte ordering
pattern and byte ordering PAD pattern.
length allowed in custom single-width configuration.
Table 1–9. Byte Ordering Pattern Length in Custom Single-Width Configuration for Stratix V
Devices
Byte Ordering Block in Double-Width Modes
In custom double-width configurations, you can program a custom byte ordering
pattern and byte ordering PAD pattern in the ALT PHY IP megafunction.
lists the byte ordering pattern length allowed in custom double-width configuration.
Table 1–10. Byte Ordering Pattern Length in Custom Double-Width Configuration for Stratix V
Devices
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO in each channel ensures reliable transfer of
data and status signals between the receiver channel and the FPGA fabric. The
receiver phase compensation FIFO compensates for the phase difference between the
parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO read
clock).
Figure 1–23
Figure 1–23. Receiver Phase Compensation FIFO
Note to
(1) These clocks may have been divided by two if a byte deserializer was used.
Custom single-width configuration with:
■
■
■
Custom double-width configuration with:
■
■
■
16-bit FPGA fabric-transceiver interface
No 8B/10B decoder
Word aligner in manual alignment mode
32-bit FPGA fabric-transceiver interface
No 8B/10B decoder (16-bit PMA-PCS interface)
Word aligner in manual alignment mode
Figure
the FPGA Fabric
Datapath to
1–23:
shows the receiver phase compensation FIFO.
rx_clkout
Configuration
Configuration
wr_clk
Compensation
Phase
FIFO
RX
rd_clk
Table 1–9
Chapter 1: Transceiver Architecture in Stratix V Devices
Byte Ordering Pattern
Pattern Length (Bits)
Length (Bits)
Byte Ordering
lists the byte ordering pattern
Last PCS Block Used
Datapath from the
8
16, 8
Parallel Recovered Clock (1)
tx_clkout (1)
coreclkout (1)
rx_coreclk (1)
May 2011 Altera Corporation
Pattern Length (Bits)
Pattern Length (Bits)
Standard PCS Architecture
Byte Ordering PAD
Byte Ordering PAD
Table 1–10
8
8