DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 417

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV52003-1.2
Input Reference Clocking
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52003-1.2
f
1
This chapter provides detailed information about the Stratix
architecture.
The clocking architecture chapter is divided into three sections:
■
■
■
Figure 2–1
Figure 2–1. Transceiver Clocking Architecture Overview
For upcoming clocking related features, refer to the
document.
Each transceiver channel has a channel PLL that can be configured as a transmitter
clock multiplier unit (CMU) PLL or receiver CDR. In a CMU PLL configuration, the
PLL uses the input reference clock to generate a serial clock. In receiver CDR
configuration, the PLL locks to the input reference clock in lock-to-reference (LTR)
mode. The ATX PLL also uses the input reference clock to synthesize a serial clock.
The input reference clock is different from the clock forwarded from the transceiver to
the FPGA fabric that clocks the transceiver logic and FPGA fabric-transceiver
interface.
“Input Reference
phase-locked loop (PLL), ATX PLL, and clock data recovery (CDR) is provided to
generate the clocks required for transceiver operation.
“Internal
transceiver.
“FPGA Fabric-Transceiver Interface
available when the transceiver interfaces with the FPGA fabric.
shows an overview of the clocking architecture.
Fabric
FPGA
Clocking”—Describes the clocking architecture internal to the
Clocking”—Describes how the reference clock to the transmit
FPGA Fabric-Transceiver
Input Reference Clock
Interface Clocks
2. Transceiver Clocking in Stratix V
Clocking”—Describes the clocking options
Transmit PLL
Transceiver
Channels
or CDR
Upcoming Stratix V Device Features
®
Internal Clocks
V transceiver clocking
Transceivers
Devices
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