DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 296

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–16
Table 9–8. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1
Active Serial Configuration (Serial Configuration Devices)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
t
t
t
t
f
t
t
t
t
t
Notes to
(1) This information is preliminary.
(2) Use these timing parameters when you use the decompression and design security features.
(3) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(4) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
(5) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to
(6) f
Symbol
DH
CH
CL
CLK
MAX
R
F
CD2UM
CD2CU
CD2UMC
“Initialization” on page
DCLK
Table
is the DCLK frequency the system is operating.
DATA[] hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency (FPP 8/16)
DCLK frequency (FPP 32)
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–8:
f
1
The AS configuration scheme is supported in 1-bit data wide (AS ×1 mode) or 4-bit
data wide (AS ×4 mode). In the AS ×1 mode, the Stratix V devices are configured
using a serial configuration device (EPCS). In the AS ×4 mode, a quad-serial
configuration device (EPCQ) configures the Stratix V devices. The AS ×4 mode
provides four times faster configuration time than the AS ×1 mode.
EPCS and EPCQ are low-cost devices with non-volatile memory that feature a simple
four-pin interface or six-pin interface, respectively, and a small form factor. These
features make the AS configuration scheme an ideal low-cost configuration solution.
If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the
nCE pin high. This causes the device to reset and tri-state the AS configuration pins.
For more information about EPCS and EPCQ devices, refer to the volume 2 of the
Configuration
AS mode supports DCLK frequency up to 100 MHz. You can choose the CLKUSR or
internal oscillator as the configuration clock source that drives DCLK. If you use the
internal oscillator as the configuration clock source, you can choose a 12.5, 25, 50, or
100 MHz clock from the Configuration panel in the Device and Pins Option settings.
9–5.
Parameter
Handbook.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
(4)
(17,408  CLKUSR
3  1/f
4 × maximum
0.45  1/f
0.45  1/f
Active Serial Configuration (Serial Configuration Devices)
DCLK period
period)
Minimum
t
CD2CU
1/f
175
—
—
—
—
DCLK
MAX
(5)
MAX
MAX
+
(6)
(Note
May 2011 Altera Corporation
Maximum
125
100
437
—
—
—
—
40
—
—
40
1),
(2)
(Part 2 of 2)
Units
MHz
MHz
ns
ns
—
—
s
s
s
s
s