DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 382

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–10
Stratix V Device Handbook Volume 3: Transceivers
DC Gain
The receiver buffers also support programmable DC gain circuitry. Unlike the
equalization circuits, the DC gain circuitry provides an equal boost to the incoming
signal across the frequency spectrum. The receiver buffer supports DC gain settings of
0, 3, 6, 9, and 12 dB.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes it using the low-speed parallel
recovered clock. It forwards the deserialized data to the receiver PCS.
■
■
■
Figure 1–9
deserialization factor.
Figure 1–9. Deserializer Operation in Single-Width Mode
In single-width mode, the deserializer supports 8- and 10-bit deserialization
factors.
In double-width mode, the deserializer supports 16- and 20-bit deserialization
factors.
In quadruple-width mode, the deserializer supports 32- and 40-bit deserialization
factors.
Parallel Recovered
Serial Recovered
Clock from CDR
Clock from CDR
shows the deserializer operation in single-width mode with a 10-bit
Received Data
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Chapter 1: Transceiver Architecture in Stratix V Devices
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
10
May 2011 Altera Corporation
To Word Aligner
PMA Architecture