DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 252

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–8
Stratix V External Memory Interface Features
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Using the RZQ Pins in a DQ/DQS Group for Memory Interfaces
DQS Phase-Shift Circuitry
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You can use the DQS/DQSn pins in some of the x4 groups as RZQ pins (listed in the
pin table). You cannot use a x4 DQ/DQS group for memory interfaces if any of its DQ
pin members are used as RZQ pins for OCT calibration.
There is no restriction on using x8/x9, x16/x18, or x32/x36 DQ/DQS groups that
include the x4 groups whose pins are used as RZQ pins because there are enough
extra pins that you can use as DQS pins.
You must manually assign DQ and DQS pins for x8, x16/x18, or x32/x36 DQ/DQS
groups whose members are used as RZQ pins. The Quartus II software might not be
able to place DQ and DQS pins without manual pin assignments, resulting in a
“no-fit”.
Stratix V devices have features that allow robust high-performance external memory
interfacing. The UniPHY megafunction allows you to use these external memory
interface features and helps set up the physical interface (PHY) best suited for your
system. This section describes each Stratix V device feature that is used in external
memory interfaces from the DQS phase-shift circuitry, DQS logic block, leveling
multiplexers, and dynamic OCT control block.
The UniPHY megafunction and the Altera memory controller MegaCore
can run at half the frequency of the I/O interface of the memory devices to allow
better timing management in high-speed memory interfaces. Stratix V devices have
built-in circuitries in the IOE to convert data from full rate (the I/O frequency) to half
rate (the controller frequency) and vice versa. If you use the Altera memory controller
MegaCore functions, the UniPHY megafunction is instantiated for you.
Implementing Altera Memory Interface IP
Stratix V phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions if the DQS/CQ and CQn pins are acting as input clocks or strobes to
the FPGA. DQS phase-shift circuitry consists of DLLs that are shared between
multiple DQS pins and the phase-offset module to further fine-tune the DQS phase
shift for different sides of the device.
For more information about the UniPHY megafunction, refer to the
of the External Memory Interface Handbook.
Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation
Volume 3:
®
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