DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 102

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–8
Figure 2–6. ECC Block for M20K
Memory Modes
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Register
Input
1
32
Table 2–5
Table 2–5. Truth Table for the ECC Status Flags
When ECC is engaged, you cannot use the byte enable feature. Also, when ECC is
engaged, read-during-write old data mode is not supported.
Figure 2–6
Stratix V embedded memory blocks allow you to implement fully synchronous
SRAM memory in multiple modes of operation. M20K blocks do not support
asynchronous memory (unregistered inputs). MLABs support asynchronous
(flow-through) read operations.
Depending on which memory block you target, you can use the following modes:
■
■
■
■
■
■
Note to
(1) eccstatus[1] corresponds to e and eccstatus[0] corresponds to ue.
Encoder
ECC
e (error)
“Single-Port RAM” on page 2–9
“Simple Dual-Port Mode” on page 2–10
“True Dual-Port Mode” on page 2–12
“Shift-Register Mode” on page 2–14
“ROM Mode” on page 2–15
“FIFO Mode” on page 2–15
0
0
1
1
Table
lists the truth table for the ECC status flags.
32
8
shows a diagram of the ECC block for M20K.
2–5:
ue (uncorrectable error)
Memory
Array
40
0
1
0
1
Optional
Register
Pipeline
40
40
No error.
Illegal.
A correctable error occurred and the error has been
corrected at the outputs; however, the memory array
has not been updated.
An uncorrectable error occurred and uncorrectable
data appears at the outputs.
(only supported on M20K)
(Note 1)
Chapter 2: Memory Blocks in Stratix V Devices
40
Status Flag
Generation
Decoder
Status
ECC
8
May 2011 Altera Corporation
2
40
Register
Memory Modes
Output