DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 466

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–10
Figure 4–8. Interlaken Channel Datapath
Stratix V Device Handbook Volume 3: Transceivers
Fabric
FPGA
rx_user_clk
1-Bit Control
64-Bit Data
tx_user_clk
1-Bit Control
64-Bit Data
Supported Features
f
CMU PLL
(From the ×1 Clock Lines)
Figure 4–8
Interlaken configurations.
Table 4–3
These functions are defined in the Interlaken Protocol Definition, Rev 1.2.
Table 4–3. Supported Features in Interlaken Configuration
For more information about Interlaken PHY IP control and status signals associated
with each feature, refer to the Interlaken PHY IP Core chapter in the
PHY IP Core User
Serial Clock
Block synchronization
64B/67B framing
±96 bits disparity maintenance
Frame synchronous scrambling and descrambling
Skip word clock compensation
Diagnostic word generation and CRC-32 checking of lane data integrity
lists the framing layer functions that are supported by Stratix V devices.
shows the PCS and PMA blocks used in the transceiver datapath for
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Guide.
Paralell Clock (Recovered)
Paralell Clock
Clock Divider
Feature
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Transmitter 10G PCS
Receiver 10G PCS
40
40
May 2011 Altera Corporation
Transmitter PMA
Receiver
Receiver PMA
Altera Transceiver
Supported
Parallel Clock
Serial Clock
Parallel and Serial Clocks
v
v
v
v
v
v
Interlaken