DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 88

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–10
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of
2 four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of 2 four-input functions.
The four LUTs share dataa and datab inputs. As shown in
signal feeds to adder0 and the carry-out from adder0 feeds to the carry-in of adder1.
The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in
arithmetic mode can drive out either registered, unregistered, or registered and
unregistered versions of the adder outputs.
Figure 1–10. ALM in Arithmetic Mode
While operating in arithmetic mode, the ALM can support simultaneous use of the
adder’s carry output along with combinational logic outputs. In this operation, adder
output is ignored. Using the adder with combinational logic output provides resource
savings of up to 50% for functions that can use this ability.
Arithmetic mode also offers clock enable, counter enable, synchronous up/down
control, add/subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up/down, and add/subtract control signals. These control signals are good
candidates for the inputs that are shared between the four LUTs in the ALM. The
synchronous clear and synchronous load options are LAB-wide signals that affect all
registers in the LAB. You can individually disable or enable these signals for each
register. The Quartus II software automatically places any registers that are not used
by the counter into other LABs.
datae0
datae1
dataf0
dataf1
datac
datab
dataa
datad
Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
carry_in
carry_out
adder0
adder1
D
D
D
D
reg0
reg1
reg2
reg3
Q
Q
Q
Q
Figure
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May 2011 Altera Corporation
1–10, the carry-in
Adaptive Logic Modules