DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 390

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–18
Standard PCS Architecture
Figure 1–16. Transceiver Datapath in Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
Fabric
(From Dedicated Input Reference Clock Pin)
FPGA
tx_clkout
rx_clkout
AC JTAG
Input Reference Clock
CMU PLL
Stratix V GX and GS devices have AC JTAG to enable board-level testing of
high-speed transceivers. AC JTAG is designed to conform to the IEEE Standard for
Boundary Scan Testing of Advanced Digital Networks (1149.6-2003). The implementation
features both AC and DC testing of the transceiver and receiver clock serial pins.
This section describes the transceiver circuit blocks available in single- and
double-width mode and within the data rate range of 600 Mbps to 8.5 Gbps.
Figure 1–16
PMA-PCS and PCS-FPGA fabric interfaces.
Serial Clock
shows the standard PCS transceiver channel datapath including the
Central/ Local Clock Divider
Parallel and Serial Clocks
Parallel Clock (Recovered)
Clock Divider
Chapter 1: Transceiver Architecture in Stratix V Devices
Transmitter PCS
Receiver PCS
May 2011 Altera Corporation
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Transmitter PMA
Standard PCS Architecture
Receiver PMA