DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 14

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–8
Stratix V Device Handbook
Table 1–4
Table 1–4. Stratix V E Device Features
Logic Elements (K)
Registers (K)
Fractional PLLs
M20K Memory Blocks
M20K Memory (MBits)
Variable Precision Multipliers (18×18)
Variable Precision Multipliers (27×27)
DDR3 SDRAM ×72 DIMM Interfaces
User I/Os, Full-Duplex LVDS
H35-F1152
F40-F1517
F45-F1932
Notes to
(1) Packages are flipchip ball grid array (1.0-mm pitch).
(2) LVDS counts are full duplex channels. Each full duplex channel is one TX pair plus one RX pair.
(3) Each package row offers pin migration (common circuit board footprint) for all devices in the row.
(4) The 1152-pin 5SEE9 and 5SEEB devices are available only in a 42.5-mm x 42.5-mm Hybrid flipchip package.
Table
lists the Stratix V E device features.
(4)
Package (1), (2),
1–4:
Features
(3)
552, 138
696, 174
840, 210
5SEE9
5SEE9
1,268
2,640
840
704
352
28
52
7
Chapter 1: Stratix V Device Family Overview
June 2011 Altera Corporation
Stratix V Family Plan
552, 138
696, 174
840, 210
5SEEB
5SEEB
1,434
2,640
950
704
352
28
52
7