DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 80

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
f
The memory LAB (MLAB) is a derivative of the Stratix V LAB. The MLAB adds
look-up table (LUT)-based SRAM capability to the LAB, as shown in
MLAB supports a maximum of 640 bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as either a 64 × 1 or a
32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple
dual-port SRAM block. MLAB and LAB blocks always coexist as pairs in all Stratix V
families. The MLAB is a superset of the LAB and includes all LAB features.
For more information about MLABs, refer to the
chapter.
Figure 1–2. LAB and MLAB Structure for Stratix V Devices
Note to
(1) You can use the MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown.
Figure
1–2:
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
Simple dual-port SRAM
LAB Control Block
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
LUT-based-64 x 1
MLAB
Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Memory Blocks in Stratix V Devices
LAB Control Block
LAB
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
ALM
May 2011 Altera Corporation
Figure
Logic Array Blocks
1–2. The