DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 110

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–16
Clocking Modes
Table 2–9. Internal Memory Clock Modes
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Independent
Input/output
Read/write
Single clock
Clocking Mode
Independent Clock Mode
Input/Output Clock Mode
Read/Write Clock Mode
1
True Dual-Port Mode
Stratix V embedded memory blocks support the following clocking modes:
■
■
■
■
Violating the setup or hold time on the memory block address registers could corrupt
memory contents. This applies to both read and write operations.
Table 2–9
Stratix V embedded memory blocks can implement independent clock mode for true
dual-port memories. In this mode, a separate clock is available for each port (clock A
and clock B). Clock A controls all registers on the port A side; clock B controls all
registers on the port B side. Each port also supports independent clock enables for
both port A and port B registers, respectively. Asynchronous clears are supported
only for output latches and output registers on both ports.
Stratix V embedded memory blocks can implement input/output clock mode for true
dual-port and simple dual-port memories. In this mode, an input clock controls all
registers related to the data input to the memory block including data, address, byte
enables, read enables, and write enables. An output clock controls the data output
registers. Asynchronous clears are available on output latches and output registers
only.
Stratix V embedded memory blocks can implement read/write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both the read and write clocks. Asynchronous clears
are available on data output latches and registers only.
“Independent Clock Mode” on page 2–16
“Input/Output Clock Mode” on page 2–16
“Read/Write Clock Mode” on page 2–16
“Single Clock Mode” on page 2–17
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lists the internal memory clock modes.
Simple Dual-Port Mode
—
v
v
v
Single-Port Mode
v
v
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Chapter 2: Memory Blocks in Stratix V Devices
ROM Mode
May 2011 Altera Corporation
v
v
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v
Clocking Modes
FIFO Mode
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