DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 353

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices
BST Operation Control
BST Operation Control
Table 11–1. 32-Bit IDCODE Information for Stratix V Devices—Preliminary
Table 11–2. JTAG Instruction Supported by Stratix V Devices (Part 1 of 2)
May 2011 Altera Corporation
Stratix V GX
Stratix V GT
Stratix V GS
Stratix V E
Notes to
(1) The MSB is on the left.
(2) The LSB of the IDCODE is always 1.
SAMPLE/PRELOAD
EXTEST
BYPASS
JTAG Instruction
Family
Table
(1)
11–1:
5SGXAB
5SGSD2
5SGSD3
5SGSD4
5SGSD5
5SGSD6
5SGSD8
5SGXA3
5SGXA4
5SGXA5
5SGXA7
5SGXA9
5SGXB5
5SGXB6
5SGTC5
5SGTC7
Table 11–1
Device
Table 11–2
5SEE9
5SEEB
Instruction Code
00 0000 0101
00 0000 1111
11 1111 1111
lists the IDCODE information for Stratix V devices.
lists the JTAG instructions that are supported by Stratix V devices.
Version
(4 Bits)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation and permits an initial data
pattern to be an output at the device pins. Also used by the
SignalTap II Embedded Logic Analyzer.
Allows the external circuit and board-level interconnects to be tested
by forcing a test pattern at the output pins and capturing test results at
the input pins.
Places the 1-bit bypass register between the TDI and TDO pins,
allowing the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation.
0010 1001 0001 0001
0010 1001 0000 0001
0010 1001 0001 0011
0010 1001 0000 0011
0010 1001 0001 0101
0010 1001 0000 0101
0010 1001 0001 0010
0010 1001 0000 0010
0010 1001 0010 0011
0010 1001 0100 0011
Part Number
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(16 Bits)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IDCODE (32 Bits)
Description
Manufacturer Identity
(1)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
(11 Bits)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
LSB (1 Bit)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(2)
1
1
1
1
1
1
1
1
1
1
11–3