DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 429

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
1
Bonded Channel Configurations
In bonded configurations, both the parallel clock and serial clock are sourced from
either the ×6 or ×N clock line. The central clock dividers source the serial clock from a
transmit PLL from the same transceiver bank using the ×1 clock line. The central clock
divider generates the parallel clock and drives both the serial clock and parallel clock
on the ×6 clock line, which can drive the ×N clock line.
Currently, the ×N clock lines are only supported for the PCIe Gen1 and Gen2 ×8
protocols.
Figure 2–11
driven by the channel PLL of channel 4 configured as a CMU PLL. The central clock
divider of channel 4 generates a parallel clock and drives both the serial clock and
parallel clock on the ×6 clock line. All bonded channels source both serial and parallel
clocks from the ×6 clock line.
shows six transmit-only channels configured in bonded configuration and
Stratix V Device Handbook Volume 3: Transceivers
2–13