DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 217
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Locations of the I/O Banks
Locations of the I/O Banks
Figure 6–2. High-Speed Differential I/Os with DPA Locations for Stratix V Devices
LVDS Channels
May 2011 Altera Corporation
1
Stratix V devices contain up to 26 I/O banks. The dedicated circuitry that supports
high-speed differential I/Os is located in the top and bottom banks.
the high-level SERDES/DPA location in the Stratix V devices.
The Stratix V device family supports LVDS on all I/O banks. Both row and column
I/Os support true LVDS input buffers with R
Alternatively, you can configure the LVDS pins as emulated LVDS output buffers that
use two single-ended output buffers with an external resistor network to support
LVDS, mini-LVDS, and RSDS standards. Stratix V devices offer single-ended I/O
reference clock support for the LVDS.
Stratix V devices support dedicated SERDES and DPA circuitry. For the supported
I/O banks, refer to
Emulated differential output buffers support tri-state capability.
General Purpose
I/O and High-Speed
LVDS I/O with
DPA and Soft CDR
Transceiver
Block
Figure
6–2.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
D
OCT and true LVDS output buffers.
Figure 6–2
shows
6–3
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