DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 284

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–4
Configuration Sequence
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Power Up
Reset
Configuration
f
1
The following sections describe the general configuration process for the FPP, AS, and
PS schemes.
To begin the configuration process, you must fully power-up all the power supplies
monitored by the POR circuitry to the appropriate voltage levels. The power supplies
must ramp-up monotonically within the specified ramp-up time to ensure successful
configuration.
All power supplies including the V
desired voltage level within the ramp-up time specification. If these supplies are not
ramped up within this specified time, your Stratix V device will not configure
successfully. If your system cannot ramp-up the power supplies within the specified
ramp-up time specification, you must hold nCONFIG low until all the power supplies
are stable.
For more information about the ramp-up time specification, refer to the
and Power-On Reset in Stratix V Devices
After power-up, the Stratix V device goes through a POR. The POR delay depends on
the MSEL settings. During POR, the device resets, holds nSTATUS low, clears the
configuration RAM bits, and tri-states all user I/O pins. After the device successfully
exits POR, all user I/O pins remain tri-stated until the device is configured.
While nCONFIG is low, the device is in reset. When the device comes out of reset,
nCONFIG must be at a logic-high level in order for the device to release the open-drain
nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the
device is ready to receive configuration data. Before and during configuration, all user
I/O pins are tri-stated. If nIO_pullup is driven low during power up and
configuration, the user I/O pins and dual-purpose I/O pins have weak pull-up
resistors, which are on after the device exits POR, before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
For more information about the POR delay specification, refer to
Specification” on page
Both nCONFIG and nSTATUS must be deasserted at a logic-high level in order for the
configuration stage to begin. For the FPP and PS configuration schemes, the device
receives configuration data on its DATA pins and the clock source on the DCLK pin.
Configuration data is latched into the Stratix V device on the rising edge of DCLK. For
the AS configuration scheme, the device receives configuration data on its AS_DATA[]
pins and drives the clock source on the DCLK pin. Configuration data is latched into
the Stratix V device on the falling edge of DCLK.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
9–2.
CCPGM
chapter.
and V
CCPD
must ramp-up from 0 V to the
May 2011 Altera Corporation
“POR Delay
Configuration Sequence
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