DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 167

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
May 2011 Altera Corporation
The Stratix V PLL can compensate multiple pad-to-input-register paths, such as a data
bus when it is set to use source-synchronous compensation mode. You can use the
“PLL Compensation” assignment in the Quartus II software Assignment Editor to
select which input pins are used as the PLL compensation targets. You can include
your entire data bus, provided the input registers are clocked by the same output of a
source-synchronous-compensated PLL. In order for the clock delay to be properly
compensated, all of the input pins must be on the same side of the device. The PLL
compensates for the input pin with the longest pad-to-register delay among all input
pins in the compensated bus.
If you do not make the “PLL Compensation” assignment, the Quartus II software
automatically selects all of the pins driven by the compensated output of the PLL as
the compensation target.
Source Synchronous Mode for LVDS Compensation
The goal of source synchronous mode is to maintain the same data and clock timing
relationship seen at the pins of the internal serializer/deserializer (SERDES) capture
register, except that the clock is inverted (180° phase shift). Thus, source synchronous
mode ideally compensates for the delay of the LVDS clock network plus any
difference in delay between these two paths:
■
■
Figure 4–22
Figure 4–22. Phase Relationship Between the Clock and Data in LVDS Mode
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift
shows an example waveform of the clock and data in LVDS mode.
Clock at the register
Data at the register
reference clock
at the input pin
Data pin
PLL
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4–27