DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 122

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

3–6
Figure 3–2. Input Register of a Variable Precision DSP Block in 18 x 18 Mode for Stratix V Devices
Note to
(1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 3–2
Figure
3–2:
shows only the data registers. Registers for the control signals are not shown.
One feature of the input register bank is to support a tap delay line; therefore, you can
drive the top leg of the multiplier input (B) from general routing or from the cascade
chain, as shown in
block supports 18-bit and 27-bit input cascading.
datab_0[17..0]
dataa_0[17..0]
datab_1[17..0]
dataa_1[17..0]
Figure 3–2
scanin[18..0]
Delay registers
Delay registers
and
Figure
Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
scanout[18..0]
3–3. The Stratix V variable precision DSP
ENA[2..0]
CLK[2..0]
ACLR[0]
Variable Precision DSP Block Resource Descriptions
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