DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 299

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Active Serial Configuration (Serial Configuration Devices)
May 2011 Altera Corporation
AS Multi-Device Configuration
1
Figure 9–7
Figure 9–7. Single Device AS ×4 Mode Configuration
Notes to
(1) Connect the pull-up resistors to V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to
(3) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum
The serial clock (DCLK) generated by the Stratix V device controls the entire
configuration cycle and provides timing for the serial interface. Stratix V devices use
an internal oscillator or external clock (CLKUSR) as the configuration clock source
(DCLK). In the AS configuration scheme, Stratix V devices drive out control signals on
the falling edge of DCLK and latch in the data on the following falling edge of DCLK.
During configuration, Stratix V devices enable the EPCS or EPCQ by driving the
nCSO output pin low, which connects to the chip select (nCS) pin of the EPCS or
EPCQ. Stratix V devices use the serial clock (DCLK) and serial data output (ASDO) pins
to send operation commands and read address signals to the EPCS or EPCQ. The
EPCS or EPCQ provides data on its serial data output (DATA[]) pin, which connects
to the AS_DATA[] input of the Stratix V devices.
For the AS multi-device configuration scheme, you can configure all devices with
different sets of configuration data (different .sof) or with the same configuration data
(same .sof). In both cases, the nCONFIG, nSTATUS, DCLK, and data line (AS_DATA1 on
the master device and DATA0 on the slave device) and CONF_DONE pins are connected
to every device in the chain. Ensure that the DCLK and data line are buffered for every
fourth device.
The AS configuration scheme supports multi-device in AS ×1 mode. The AS ×4 mode
does not support multi-device configuration setup.
Table 9–4 on page
frequency specification is 100 MHz.
Quad-Serial Configuration
Figure
shows the single-device configuration setup for an AS ×4 mode.
Device
9–7:
DATA0
DATA1
DATA2
DATA3
9–7.
DCLK
nCS
V
CCPGM (1)
CCPGM
10 kΩ
V
CCPGM (1)
at 3.0-V supply.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
10 kΩ
V
CCPGM (1)
GND
10 kΩ
nCONFIG
nSTATUS
CONF_DONE
nCE
AS_DATA0/
ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCSO
Stratix V Device
MSEL[4..0]
CLKUSR
nCEO
N.C.
(2)
(3)
9–19