DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 97

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Overview
Table 2–2. Memory Capacity and Distribution in Stratix V Devices (Part 2 of 2)
May 2011 Altera Corporation
Stratix V E
Family
Embedded Memory Block Types
Parity Bit Support
Byte Enable Support
Device
5SEEB
5SEE9
M20K memory blocks are dedicated resources. MLABs are dual-purpose blocks. You
can configure the MLABs as regular logic array blocks (LABs) or as MLABs. Ten
adaptive logic modules (ALMs) make up one MLAB. You can configure each ALM in
an MLAB as either a 64 x 1 or a 32 x 2 block, resulting in a 64 x 10 or a 32 x 20 simple
dual-port SRAM block in a single MLAB.
On MLABs, the ninth bit associated with each byte can store a parity bit or serve as an
additional data bit. No parity function is actually performed on the ninth bit.
The M20K supports one parity bit per 4-data bits when the data width is 5, 10, 20, or
40. The parity bits for inputs and outputs are bit 4, 9, 14, 19, 24, 29, 34, and 39. When
writing or reading with non-parity widths, these bits are skipped. No parity function
is performed on bit 4, 9, 14, 19, 24, 29, 34, and 39.
All embedded memory blocks support byte enables that mask the input data so that
only specific bytes of data are written. The unwritten bytes retain the previously
written values. The write enable (wren) signals, along with the byte enable (byteena)
signals, control the write operations of the RAM blocks.
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers do not have a
clear port. When using parity bits on the M20K blocks, the byte enable controls ten
bits (eight bits of data plus two parity bits). When using parity bits on the MLAB, the
byte enable controls all ten bits in the widest mode. Byte enables operate in a one-hot
fashion, with the LSB of the byteena signal corresponding to the LSB of the data bus.
The byte enables are active high.
Table 2–3
Table 2–3. byteena Controls in x40 Data Width
byteena[3..0]
1111(default)
1000
0100
0010
0001
MLABs
15,850
15,850
lists the byteena controls in the x40 data width.
M20K Blocks
[39:30]
[39:30]
2,640
2,640
—
—
—
Total Dedicated RAM Bits
(M20K Blocks Only) (Mb)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
[29:20]
[29:20]
—
—
—
51.6
51.6
Data Bits Written
[19:10]
[19:10]
—
—
—
Total RAM Bits (Including
LABs) (Mb)
61.2
61.2
[9:0]
[9:0]
—
—
—
2–3