DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 95

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV51003-1.2
Overview
Table 2–1. Summary of Memory Features in Stratix V Devices (Part 1 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51003-1.2
Maximum performance
Total RAM bits (including parity bits)
Configurations (depth x width)
Parity bits
Byte enable
Packed mode
Address clock enable
Single-port memory
Feature
Embedded memory blocks include 640-bit enhanced memory logic array blocks
(MLABs) and 20-Kbit M20K blocks. This chapter describes the embedded memory
blocks in Stratix
embedded SRAM to address the Stratix V device design requirements efficiently.
MLABs are optimized to implement shift registers for digital signal processing (DSP)
applications, wide shallow FIFO buffers, and filter delay lines. You can use the M20K
blocks to support larger memory configurations and include error correction code
(ECC).
This chapter contains the following sections:
■
■
■
■
Table 2–1
“Overview” on page 2–1
“Memory Modes” on page 2–8
“Clocking Modes” on page 2–16
“Design Considerations” on page 2–17
lists the features supported by the embedded memory blocks.
®
V devices. Embedded memory blocks provide different sizes of
2. Memory Blocks in Stratix V Devices
600 MHz
64 x 10
32 x 16
32 x 18
32 x 20
MLABs
64 x 8
64 x 9
640
v
v
v
v
—
600 MHz
512 x 32
512 x 40
16K x 1
2K x 10
1K x 16
1K x 20
20,480
8K x 2
4K x 4
4K x 5
2K x 8
M20K
v
v
v
v
v
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