DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 395

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
Table 1–8. Received Bit Order for the Bit Reversal Feature for Stratix V Devices
May 2011 Altera Corporation
Not enabled (default)
Enabled
Receiver Bit Reversal
Feature
Programmable Run Length Violation Detection
The programmable run length violation circuit resides in the word aligner block and
detects consecutive 1s or 0s in the data. If the data stream exceeds the preset
maximum number of consecutive 1s or 0s, the violation is signified by the assertion of
the rx_rlv status bit.
Table 1–7
Table 1–7. Detection Capabilities of the Run Length Violation Circuit for Stratix V Devices
Receiver Polarity Inversion
The positive and negative signals of a serial differential link are often erroneously
swapped during board layout. Solutions such as board re-spin or major updates to the
PLD logic can be expensive. The receiver polarity inversion feature is provided to
correct this situation.
Receiver Bit Reversal
By default, the receiver assumes a LSB-to-MSB transmission. If the transmission order
is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel data to the
FPGA fabric on rx_parallel_data. The receiver bit reversal feature is available to
correct this situation.
Flipping the parallel data using this feature allows the receiver to forward the correct
bit-ordered data to the FPGA fabric on rx_parallel_data in the case of an
MSB-to-LSB transmission.
Table 1–8
enabled.
Single-width mode
Double-width mode
LSB to MSB
MSB to LSB
For example:
■
■
8-bit—D[7:0]rewired to D[0:7]
10-bit—D[9:0]rewired to D[0:9]
lists the detection capabilities of the run length violation circuit.
lists the transmission bit order with and without the receiver bit reversal
Mode
Single-Width Mode
(8 or 10 Bit)
PMA-PCS Interface
Width (Bits)
10
16
20
8
LSB to MSB
MSB to LSB
For example:
■
■
16-bit—D[15:0]rewired to D[0:15]
20-bit—D[19:0]rewired to D[0:19]
Stratix V Device Handbook Volume 3: Transceivers
Run Length Violation Detector Range
Minimum
Double-Width Mode
10
4
5
8
(16 or 20 Bit)
Maximum
128
160
512
640
1–23