DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 393

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
Table 1–5. Word Aligner Options Available for Stratix V Devices
May 2011 Altera Corporation
Custom
Single-Width
Custom
Double-Width
PCIe
Configuration
PMA-PCS
Interface
Width
(Bits)
10
16
20
10
8
In addition to restoring the word boundary, the word aligner also implements the
following features:
Depending on the configuration, the word aligner operates in one of the following
three modes:
Table 1–5
Synchronization state machine in configurations such as PCIe
Programmable run length violation detection in all configurations
Receiver polarity inversion in all configurations except PCIe
Receiver bit reversal in custom single-width and custom double-width
configurations
Receiver byte reversal in custom double-width configurations
Manual alignment
Automatic synchronization state machine
Bit-slip
Word Alignment
State Machine
State Machine
State Machine
Synchronized
Synchronized
Synchronized
Alignment
Alignment
Automatic
Alignment
Alignment
Automatic
Automatic
Manual
Bit-Slip
Manual
Bit-Slip
Manual
Bit-Slip
Manual
Bit-Slip
Mode
lists the available word aligner options.
Pattern Length
7 and 10 bits
7 and 10 bits
7 and 10 bits
8, 16, and 32
8, 16, and 32
7, 10, and 20
7, 10, and 20
7 and 10 bits
Alignment
16 bits
16 bits
10 bits
Word
bits
bits
bits
bits
User-controlled signal starts the alignment process.
Alignment happens once unless the signal is re-asserted.
User-controlled signal shifts data one bit at a time.
User-controlled signal starts the alignment process.
Alignment happens once unless the signal is re-asserted.
User-controlled signal shifts data one bit at a time.
Data is required to be 8B/10B encoded. Aligns to the
selected word aligner pattern.
User-controlled signal starts the alignment process.
Alignment happens once unless the signal is re-asserted.
User-controlled signal shifts data one bit at a time.
User-controlled signal starts the alignment process.
Alignment happens once unless the signal is re-asserted.
User-controlled signal shifts data one bit at a time.
Data is required to be 8B/10B encoded. Aligns to the
selected word aligner pattern.
Automatically selected word aligner pattern length and
pattern.
Word Alignment Behavior
Stratix V Device Handbook Volume 3: Transceivers
1–21

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