DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 346

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

10–8
Table 10–7. Error Detection Registers (Part 2 of 2)
Error Detection Timing
Table 10–8. Minimum and Maximum Error Detection Frequencies
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
User Update Register
JTAG Shift Register
User Shift Register
JTAG Fault Injection
Register
Fault Injection Register
Device Type
Stratix V
Register
Error Detection
When you enable the error detection CRC feature through the Quartus II software, the
device automatically activates the CRC error detection process after entering user
mode.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the error
location search, after the EMR is updated. At the end of this cycle, the CRC_ERROR pin is
pulled low for a minimum of 32 clock cycles. If the next frame contains an error,
CRC_ERROR is driven high again after the EMR is overwritten by the new value. You
can start to unload the error message on each rising edge of the CRC_ERROR pin. Error
detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency.
detection frequencies.
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to
(2), where n is between 1 and 8. The divisor ranges from 2 through 256
(Equation
Equation 10–1.
100 MHz/2
Frequency
This 67-bit register is automatically updated with the contents of the EMR one cycle after this
register content is validated. It includes a clock enable, which must be asserted prior to being
sampled into the user shift register. This requirement ensures that the user update register is not
being written into by the contents of the EMR at exactly the same time that the user shift register is
reading its contents.
This 67-bit register is accessible by the JTAG interface and allows the contents of the JTAG update
register to be sampled and read out by SHIFT_EDERROR_REG JTAG instruction.
This 67-bit register is accessible by the core logic and allows the contents of the user update
register to be sampled and read by user logic.
This 47-bit register is fully controlled by the EDERROR_INJECT JTAG instruction. This register
holds the information of the error injection that you want in the bitstream.
The content of the JTAG fault injection register is loaded into this 47-bit register when it is
updated.
1
n
The error detection frequency reflects the frequency of the error detection
process for a frame because the CRC calculation in Stratix V devices is done
on a per-frame basis.
10–1).
Detection Frequency
“Software Support” on page
Maximum Error
50 MHz
Error Detection Frequency
Table 10–8
Description
Minimum Error Detection
lists the minimum and maximum error
Frequency
390 KHz
10–11). The divisor is a power of two
Chapter 10: SEU Mitigation in Stratix V Devices
=
100MHz
---------------------- -
2
n
May 2011 Altera Corporation
1, 2, 3, 4, 5, 6, 7, 8
Valid Divisors (n)
Error Detection Timing