DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 108

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–14
Figure 2–13. True Dual-Port Timing Waveform
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
q_a (asynch)
q_b (asynch)
address_a
address_b
data_a
Shift-Register Mode
wren_a
rden_a
wren_b
rden_b
clk_a
clk_b
din-1
an-1
doutn-1
Figure 2–13
and the read operation at port B, with the Read-During-Write behavior set to new
data. Registering the RAM outputs delay the q outputs by one clock cycle.
All Stratix V memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for DSP applications, such as finite
impulse response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto- and cross-correlation functions. These and other DSP applications
require local data storage, traditionally implemented with standard flipflops that
exhaust many logic cells for large shift registers. Alternatively, you can use embedded
memory as a shift-register block to save logic cell and routing resources.
The input data width (w), the length of the taps (m), and the number of taps (n)
determine the size of a shift register (w x m x n). You can cascade memory blocks to
implement larger shift registers.
bn
din-1
din
an
shows true dual-port timing waveforms for the write operation at port A
doutn
din
b0
a0
dout0
a1
dout0
dout1
b1
a2
dout2
a3
Chapter 2: Memory Blocks in Stratix V Devices
dout3
dout1
b2
din4
a4
din4
May 2011 Altera Corporation
din5
a5
dout2
din5
b3
din6
a6
Memory Modes