DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 230

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–16
Figure 6–15. Receiver Data Realignment Rollover
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
rx_channel_data_align
rx_cda_max
rx_outclock
rx_inclock
■
Figure 6–14
deserialization factor set to 4.
Figure 6–14. Data Realignment Timing
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set equal to or greater than the deserialization factor, allowing enough depth in the
word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the MegaWizard Plug-In Manager. An optional status port,
RX_CDA_MAX, is available to the FPGA fabric from each channel to indicate when the
preset rollover point is reached.
Figure 6–15
rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has
occurred.
Valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN.
rx_channel_data_align
shows receiver output (RX_OUT) after one bit slip pulse with the
shows a preset value of four bit-times before rollover occurs. The
rx_outclock
rx_inclock
rx_out
rx_in
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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