DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 210

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–34
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
f
1
For more information about the RSDS I/O standard, refer to the RSDS Specification
available on the National Semiconductor website (www.national.com).
Mini-LVDS
Stratix V devices support the true mini-LVDS output standard with data rates up to
400 Mbps using LVDS output buffer types on all I/O banks. Emulated mini-LVDS
output buffers use two single-ended output buffers with external three-resistor
networks and can be tri-stated. They are available in all I/O banks (refer to
Figure
Figure 5–21. Emulated Mini-LVDS I/O Standard Termination
Note to
(1) The R
A resistor network is required to attenuate the LVDS output voltage swing to meet
the mini-LVDS specifications. You can modify the three-resistor network values to
reduce power or improve noise margin. The resistor values chosen must satisfy
Equation 5–1 on page
Altera recommends performing simulations using IBIS or SPICE models to validate
that custom resistor R
Termination
Termination
On-Board
External
Figure
5–21).
OCT
S
and R
5–21:
P
values are pending characterization.
S
5–33.
Transmitter
Transmitter
and R
P
values meet the mini-LVDS requirements.
External Resistor
External Resistor
Three-Resistor Network (RSDS_E_3R)
≤
≤
1 inch
1 inch
R
R
R
R
S
S
S
S
R
R
P
P
50 Ω
50 Ω
50 Ω
50 Ω
Chapter 5: I/O Features in Stratix V Devices
(Note 1)
100 Ω
Termination Schemes for I/O Standards
100 Ω
May 2011 Altera Corporation
Stratix V OCT
Receiver
Receiver