DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 113

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Design Considerations
Figure 2–17. Mixed-Port Read-During-Write—Old Data Mode
May 2011 Altera Corporation
q_b (asynch)
f
address_a
byteena_a
address_b
clk_a&b
wren_a
rden_b
data_a
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock.
In this mode, you also have two output choices—“old data” or “don’t care”. In old
data mode, a read-during-write operation to different ports causes the RAM outputs
to reflect the “old data” value at that address location. In don’t care mode, the same
operation results in a “don’t care” or “unknown” value on the RAM outputs.
The RAM MegaWizard Plug-In Manager controls the read-during-write behavior. For
more information, refer to the
Guide.
Figure 2–17
behavior for old data mode.
shows a sample functional waveform of mixed-port read-during-write
AAAA
A0(old data)
BBBB
A0
A0
AAAA
Internal Memory (RAM and ROM) Megafunction User
CCCC
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
BBBB
11
DDDD
A1(old data)
EEEE
A1
A1
DDDD
FFFF
EEEE
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