DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 253

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
Figure 7–4. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry
Note to
(1) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
(2) This transceiver block is applicable to all Stratix V devices except for Stratix V E devices.
May 2011 Altera Corporation
Figure
7–4:
Phase-Shift
Phase-Shift
Reference
Reference
Circuitry
Circuitry
Clock
DQS
Clock
DQS
DLL
DLL
Figure 7–4
CQn pins in the device, where memory interfaces are supported on all sides of the
Stratix V device. For possible reference input clock pins for each DLL, refer to
“Delay-Locked Loop” on page
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. DQS logic blocks allow the DQS delay settings to be updated
concurrently at every DQS/CQ or CQn pin.
to IOE
CQn
Pin
Δt
DQS/CQ
shows how the DQS phase-shift circuitry is connected to the DQS/CQ and
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
CQn
to IOE
Pin
Δt
7–10.
DQS Logic
Blocks
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
to IOE
CQn
(Note 1)
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
to IOE
CQn
Pin
Δt
Phase-Shift
Reference
Phase-Shift
Reference
Circuitry
Circuitry
Clock
DLL
Clock
DLL
DQS
DQS
7–9