DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 180

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–4
Table 5–2. Stratix V I/O Standards and Voltage Levels
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Differential SSTL-18 Class II
Differential SSTL-15 Class I
Differential SSTL-15 Class II
Differential HSTL-18 Class I
Differential HSTL-18 Class II
Differential HSTL-15 Class I
Differential HSTL-15 Class II
Differential HSTL-12 Class I
Differential HSTL-12 Class II
Differential SSTL-15
Differential SSTL-135
Differential SSTL-125
Differential SSTL-12
Differential HSUL-12
LVDS (6),
RSDS (6),
mini-LVDS (6),
LVPECL
Notes to
(1) V
(2) For more information about the 3.3-V LVTTL/LVCMOS I/O standard supported in Stratix V devices, refer to
(3) Single-ended HSTL/SSTL/HSUL, differential SSTL/HSTL/HSUL, and LVDS input buffers are powered by V
(4) Typically this I/O standard does not require board termination.
(5) The LVPECL I/O standard is supported for input clock operation. Differential clock input buffers are powered by V
(6) All I/O banks support true LVDS, RSDS, and mini-LVDS I/O standards using true LVDS output buffers without resistor networks. All I/O banks also
(7) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_3R, RSDS_E_3R, and mini_LVDS_E_3R.
HSUL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as inverted. Differential
HSTL, SSTL, and HSUL inputs use LVDS differential input buffers with R
support emulated LVDS, RSDS, and mini-LVDS I/O standards using two single-ended output buffers with a three-resistor (LVDS_E_3R,
RSDS_E_3R, and mini-LVDS_E_3R) network.
CCPD
Table
I/O Standard
is either 2.5 or 3.0 V. For V
(7)
(7)
5–2:
(7)
CCIO
Standard Support
ANSI/TIA/EIA-644
= 3.0 V, V
JESD79-3D
JESD8-16A
JESD8-16A
JESD8-15
JESD8-6
JESD8-6
JESD8-6
JESD8-6
—
—
—
—
—
—
—
—
—
CCPD
= 3.0 V. For V
(Note 1)
Operation
Input
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(5)
CCIO
V
= 2.5 V or less, V
D
(Part 2 of 2)
CCIO
support.
(V)
Operation
Output
1.35
1.25
1.8
1.5
1.5
1.8
1.8
1.5
1.5
1.2
1.2
1.5
1.2
1.2
2.5
2.5
2.5
—
CCPD
= 2.5 V.
(Pre-Driver
Chapter 5: I/O Features in Stratix V Devices
V
Voltage)
CCPD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
(V)
CCPD
“3.3-V I/O Interface” on page
. Differential HSTL, SSTL, and
May 2011 Altera Corporation
(Input Ref
CCPD
Voltage)
V REF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
.
(V)
I/O Standard Support
Termination
Voltage)
(Board
V TT
0.90
0.75
0.75
0.90
0.90
0.75
0.75
0.60
0.60
(4)
(4)
(4)
(4)
(4)
—
—
—
—
(V)
5–10.