DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 258

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–14
Figure 7–5. Simplified Diagram of the DQS Phase-Shift Circuitry
Notes to
(1) All features of the DQS phase-shift circuitry are accessible from the UniPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array, DQS logic block, and read FIFO block.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Input Reference
to
Clock (2)
Table 7–3
Figure
7–5:
clk
through
1
DLL
Table
Figure 7–5
into the DLL to a chain of up to eight delay elements. The phase comparator compares
the signal coming out of the end of the delay chain block to the input reference clock.
The phase comparator then issues the upndn signal to the Gray-code counter. This
signal increments or decrements a seven-bit delay setting (DQS delay settings) that
increases or decreases the delay through the delay element chain to bring the input
reference clock and the signals coming out of the delay element chain in phase.
In the Quartus II assignment, the phase offset control block ‘A’ is designated as
DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N1 and phase offset control block ‘B’ is
designated as DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N2.
You can reset the DLL from either the logic array or a user I/O pin (when 2,560 or
512 clock cycles applies). Each time the DLL is reset, you must wait for 2,560
(low-jitter mode) or 512 clock cycles for the DLL to lock before you can capture the
data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 45°, 90°, 135°, or 180°. The shifted DQS signal is then used as the clock for the
DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a
45° phase shift on DQS2T, referenced from a 200-MHz clock. However, not all
phase-shift combinations are supported. The phase shifts on the DQS pins referenced
by the same DLL must all be a multiple of 45° (up to 180°).
Comparator
aload
7–6.
Phase
Delay Chains
upndninclkena
shows a simple block diagram of the DLL. The input reference clock goes
upndnin
Up/Down
Counter
7
7
offsetdelayctrlout [6:0]
offsetdelayctrlout [6:0]
delayctrlout [6:0]
dqsupdate
(Note 1)
Chapter 7: External Memory Interfaces in Stratix V Devices
offsetdelayctrlin [6:0]
offsetdelayctrlin [6:0]
7
DQS Delay
Settings
addnsub
addnsub
Stratix V External Memory Interface Features
Phase offset settings
from the logic array
Phase offset settings
from the logic array
( offset [6:0] )
(4)
7
7
(dll_offset_ctrl_b)
(dll_offset_ctrl_a)
Control
Control
Phase
Phase
Offset
Offset
B
A
May 2011 Altera Corporation
( offset [6:0] )
7
7
Phase offset
settings to DQS pin
on left or right edge (3)
( offsetctrlout [6:0] )
Phase offset
settings to DQS pins
on top or bottom edge (3)
( offsetctrlout [6:0] )