DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 289

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Fast Passive Parallel Configuration
Fast Passive Parallel Configuration
May 2011 Altera Corporation
DCLK-to-DATA[] Ratio for FPP configuration
f
f
1
Use the data in
configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf)
format, have different file sizes. For the different types of configuration file and file
sizes, refer to the Quartus II software. However, for a specific version of the Quartus II
software, any design targeted for the same device has the same uncompressed
configuration file size. If you are using compression, the file size can vary after each
compilation because the compression ratio depends on your design.
For more information about setting device configuration options or creating
configuration files, refer to the
Formats
The FPP configuration using an external host provides the fastest method to configure
Stratix V devices. FPP is supported in multiple data widths—8-bits, 16-bits, and
32-bits. You can perform a FPP configuration of Stratix V devices using an external
host such as a MAX II device or microprocessor. The external host controls the transfer
of configuration data from a storage device, such as flash memory, to the target
Stratix V device. You can store configuration data in .rbf, .hex, or .ttf formats.
Therefore, the design that controls the configuration stages, such as fetching the data
from flash memory and sending it to the device, must be stored in the MAX II device
or microprocessor.
The Parallel Flash Loader (PFL) feature in MAX II devices provides an efficient
method to program CFI flash memory devices through the JTAG interface. PFL also
acts as a controller to read configuration data from the flash memory device and
configures the Stratix V device. PFL supports both the PS and FPP configuration
schemes.
For more information about the PFL, refer to
Guide.
Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device for both uncompressed and compressed configuration data
in a FPP configuration.
FPP configuration requires a different DCLK-to-DATA[]ratio when you enable the
design security, decompression, or both features.
DCLK-to-DATA[]ratio for each combination.
Table 9–6. DCLK-to-DATA[] Ratio
FPP ×8
Configuration
Scheme
chapters in volume 2 of the Configuration Handbook.
Table 9–5
Disabled
Disabled
Enabled
Enabled
Decompression
to estimate the file size before design compilation. Different
(Note 1)
Device Configuration Options
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(Part 1 of 2)
Parallel Flash Loader Megafunction User
Disabled
Enabled
Disabled
Enabled
Design Security
Table 9–6
and
lists the
Configuration File
DCLK-to-DATA[]
Ratio
1
1
2
2
9–9