DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 344

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

10–6
Error Detection Block
Table 10–6. Two Types of CRC Detection
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
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This is the CRAM error checking ability (32-bit error
detection CRC) during user mode for use by the
CRC_ERROR pin.
For each frame of data, the pre-calculated 32-bit error
detection CRC enters the CRC circuit at the end of the
frame data and determines whether there is an error or
not.
If an error occurs, the search engine finds the location
of the error.
The error messages can be shifted out through the
JTAG instruction or core interface logics while the
error detection block continues running.
The JTAG interface reads out the 32-bit error detection
CRC result for the first frame and also shifts the 32-bit
error detection CRC bits to the 32-bit error detection
CRC storage registers for test purposes.
You can deliberately introduce single error or
double-adjacent error to the configuration memory for
testing and design verification.
User Mode CRC Error Detection
1
The error detection block contains the logic necessary to calculate the 32-bit error
detection CRC signature for the configuration CRAM bits in the Stratix V device.
The CRC circuit continues running even if an error occurs. When a CRC error occurs,
the device sets the CRC_ERROR pin high.
that check the configuration bits.
The
detection.
“Error Detection Registers”
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section focuses on the user mode CRC error
This is the 16-bit configuration CRC that is embedded in
every configuration data frame.
During configuration, after a frame of data is loaded into the
Stratix V device, the pre-computed configuration CRC is
shifted into the CRC circuitry.
At the same time, the 16-bit configuration CRC value for the
data frame shifted-in is calculated. If the pre-computed
configuration CRC and calculated configuration CRC values
do not match, nSTATUS is set low. Every data frame has a
16-bit configuration CRC; therefore, there are many 16-bit
configuration CRC values for the whole configuration
bitstream as there are many data frames. Every device has
different lengths of the configuration data frame.
Table 10–6
Configuration CRC Error Detection
lists the two types of CRC detection
Chapter 10: SEU Mitigation in Stratix V Devices
May 2011 Altera Corporation
Error Detection Block