DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 32

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Electrical Characteristics
Table 2–4. Transceiver Power Supply Operating Conditions for Stratix V GX and GS Devices—Preliminary
May 2011 Altera Corporation
V
V
V
V
V
V
V
V
V
V
V
V
Notes to
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
(2) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps. Up to 6.5 Gbps, you can connect this supply
CCA_GXBL
CCA_GXBR
CCHIP_L
CCHIP_R
CCHSSI_L
CCHSSI_R
CCR_GXBL
CCR_GXBR
CCT_GXBL
CCT_GXBR
CCH_GXBL
CCH_GXBR
you can connect this supply to either 3.0 V or 2.5 V.
to either 1.0 V or 0.85 V.
Symbol
Table
(2)
(1)
(2)
(2)
(1)
(2)
2–4:
f
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Transceiver PCS power (left side)
Transceiver PCS power (right side)
Receiver power (left side)
Receiver power (right side)
Transmitter power (left side)
Transmitter power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
Table 2–4
Stratix V GX and GS devices.
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
For more information about power estimation tools, refer to the
Estimator User Guide
Handbook.
I/O Pin Leakage Current
Table 2–5
Table 2–5. I/O Pin Leakage Current for Stratix V Devices—Preliminary
I
I
I
OZ
Symbol
lists the transceiver power supply recommended operating conditions for
lists the Stratix V I/O pin leakage current specifications.
Input pin
Tri-stated I/O pin
Description
Description
and the
PowerPlay Power Analysis
V
V
I
O
= 0 V to V
= 0 V to V
Conditions
CCIOMAX
Stratix V Device Handbook Volume 1: Overview and Datasheet
CCIOMAX
2.85, 2.375
0.82, 0.95
0.82, 0.95
Minimum
1.425
0.82
0.82
chapter in the Quartus II
Min
-30
-30
0.85, 1.0
0.85, 1.0
Typical
3.0, 2.5
0.85
0.85
1.5
PowerPlay Early Power
Typ
—
—
3.15, 2.625
0.88, 1.05
0.88, 1.05
Maximum
1.575
0.88
0.88
Max
30
30
Unit
Unit
µA
µA
V
V
V
V
V
V
2–4