DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 345

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 10: SEU Mitigation in Stratix V Devices
Error Detection Block
Figure 10–2. Error Detection Circuitry, Syndrome Registers, and Error Injection Block
Table 10–7. Error Detection Registers (Part 1 of 2)
May 2011 Altera Corporation
Syndrome Register
Error Message
Register
JTAG Update Register
Register
Readback
bitstream with
expected CRC
included
Error Detection Registers
Error Injection Block
Injection Register
Fault Injection
JTAG Fault
There is one set of 32-bit registers in the error detection circuitry that stores the
computed CRC signature. A non-zero value on the syndrome register causes the
CRC_ERROR pin to be set high.
Figure 10–2
block.
Table 10–7
Register
This 32-bit register contains the CRC signature of the current frame through the error detection
verification cycle. The CRC_ERROR signal is derived from the contents of this register.
This 67-bit register contains information on the error type, location of the error, and the actual
syndrome. The types of errors and location reported are single- and double-adjacent bit errors.
The location bits for other types of errors are not identified by the EMR. The content of the register
is shifted out through the SHIFT_EDERROR_REG JTAG instruction or to the core through the core
interface.
This 67-bit register is automatically updated with the contents of the EMR one cycle after this
register content is validated. It includes a clock enable, which must be asserted prior to being
sampled into the JTAG shift register. This requirement ensures that the JTAG Update Register is
not being written into by the contents of the EMR at the same time that the JTAG shift register is
reading its contents.
Error Detection
State Machine
lists the registers shown in
shows the error detection circuitry, syndrome registers, and error injection
Control Signals
JTAG Update
JTAG TDO
JTAG Shift
Register
Register
32-Bit Error Detection CRC
Calculation, Error
Search Engine, and
Internal Scrubbing
Error Message
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Register
Figure
Description
General Routing
User Update
User Shift
Register
Register
10–2.
Syndrome
Register
CRC_ERROR
10–7