DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 408

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–36
Stratix V Device Handbook Volume 3: Transceivers
1
Figure 1–32
Figure 1–32. Descrambler
Frame Synchronous Mode
Use frame synchronous mode in the Interlaken configuration only. When block
synchronization is achieved, the descrambler uses the scrambler seed from the
received scrambler state word. This block also forwards the current descrambler state
to the frame synchronizer.
Self Synchronous Mode
Use self synchronous mode in the 10GBASE-R configuration.
Frame Synchronizer
The frame synchronizer block is supported in the Interlaken configuration only.
The frame synchronizer block obtains lock by looking for four synchronization words
in consecutive metaframes. After synchronization, it monitors the scrambler word in
the metaframe and de-asserts the lock signal after three consecutive mismatches and
starts the synchronization process again. The lock status is available to the FPGA
fabric.
The frame synchronizer is only used in the Interlaken configuration.
Figure 1–33
Figure 1–33. Frame Synchronizer
Data to CRC-32
Checker
shows the descrambler.
shows the frame synchronizer.
10GBASE-R Configuration
Interlaken Configuration
Frame Synchronizer in
Descrambler Data to
64B/66B Decoder in
Descrambler Data to
Synchronous
Synchronous
Descrambler
Descrambler
Synchronizer
(Frame
Mode)
Mode)
(Self
Frame
Chapter 1: Transceiver Architecture in Stratix V Devices
Data from Block Synchronizer
in 10GBASE-R Configuration
Data from Disparity Checker
in Interlaken Configuration
in Interlaken Configuration
Data from Descrambler
May 2011 Altera Corporation
10G PCS Architecture