DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 241

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Source-Synchronous Timing Budget
May 2011 Altera Corporation
1
For LVDS receivers, the Quartus II software provides an RSKM report showing the
SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by
executing the report_RSKM command in the TimeQuest Timing Analyzer. You can find
the RSKM report in the Quartus II compilation report in the TimeQuest Timing
Analyzer section.
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver
through the TimeQuest Timing Analyzer constraints menu.
For assigning an input delay, follow these steps:
1. The Quartus II TimeQuest Timing Analyzer GUI has many options for setting the
Figure 6–25. Selection of Constraints Menu in TimeQuest Timing Analyzer
constraints and analyzing the design.
the Constraints menu. For setting an input delay, you must select the Set Input
Delay option.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 6–25
shows various commands on
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