DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 237

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Source-Synchronous Timing Budget
May 2011 Altera Corporation
Differential Data Orientation
Differential I/O Bit Position
Instead of focusing on clock-to-output and setup times, source synchronous timing
analysis is based on the skew between the data and the clock signals. High-speed
differential data transmission requires the use of timing parameters provided by IC
vendors and is strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation timing
parameters, the timing budget definitions for the Stratix V device family, and how to
use these timing parameters to determine a design’s maximum performance.
There is a set relationship between an external clock and the incoming data. For
operations at 1 Gbps and a serialization factor of 10, the external clock is multiplied by
10. You can set phase-alignment in the PLL to coincide with the sampling window of
each data bit. The data is sampled on the falling edge of the multiplied clock.
Figure 6–22
Figure 6–22. Bit Orientation in the Quartus II Software
Data synchronization is necessary for successful data transmission at high
frequencies.
figure is based on the following:
■
■
■
Serialization factor equals the clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
shows the data bit orientation of the x10 mode.
Figure 6–23
inclock/outclock
data in
shows the data bit orientation for a channel operation. This
MSB
9
8
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
7
6
10 LVDS Bits
5
4
3
2
1
LSB
0
6–23