DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 205

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
Figure 5–15. Differential SSTL I/O Standard Termination
Note to
(1) This is not applicable for differential SSTL-12, differential SSTL-15, differential SSTL-125, differential SSTL-135, and differential HSUL-12 I/O
May 2011 Altera Corporation
Termination
Termination
On-Board
External
OCT
standards.
Figure
Stratix V
Series OCT 50 Ω
5–15:
Transmitter
Transmitter
1
Differential HSTL, SSTL, and HSUL I/O standard outputs are not true differential
outputs. They use two single-ended outputs with the second output programmed as
inverted.
25 Ω
25 Ω
Differential SSTL Class I
Z
Z
0
0
= 50 Ω
= 50 Ω
50 Ω
50 Ω
V
50 Ω
GND
CCIO
100 Ω
100 Ω
V
TT
V
TT
V
GND
50 Ω
CCIO
Receiver
100 Ω
100 Ω
Receiver
(Note 1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Stratix V
Series OCT 25 Ω
Transmitter
Transmitter
50 Ω
25 Ω
25 Ω
V
V
TT
TT
50 Ω
50 Ω
V
TT
Z
Z
0
0
V
= 50 Ω
= 50 Ω
TT
50 Ω
Differential SSTL Class II
50 Ω
50 Ω
50 Ω
V
GND
CCIO
100 Ω
100 Ω
V
TT
V
TT
V
GND
50 Ω
CCIO
Receiver
100 Ω
100 Ω
Receiver
5–29