DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 481

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
PCI Express (PCIe)—Gen1 and Gen2
May 2011 Altera Corporation
PIPE ×4 Configuration
Figure 4–17
within the PCS is independent for each receiver channel. Clocking is bonded only for
transmit channels, whereas the control signals are bonded for both transmit and
receive channels. The Quartus II software automatically places the clock generator
and master channel in either channel 1 or channel 4 within a transceiver bank, as
shown in
Figure
shows transmitter clocking for a PIPE ×4 bonded configuration. Clocking
4–18.
Stratix V Device Handbook Volume 3: Transceivers
4–25