DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 153

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Clock Networks in Stratix V Devices
May 2011 Altera Corporation
Clock Output Connections
Clock Control Block
f
For Stratix V PLL connectivity to GCLK and RCLK networks, refer to
to GCLK and RCLK Networks for Stratix V
Every GCLK, RCLK, and PCLK network has its own clock control block. The control
block provides the following features:
■
■
■
Figure
blocks, respectively.
You can select the clock source for the GCLK select block either statically or
dynamically. You can statically select the clock source using a setting in the Quartus II
software or you can dynamically select the clock source using internal logic to drive
the multiplexer-select inputs. When selecting the clock source dynamically, you can
select either PLL outputs (such as C0 or C1) or a combination of clock pins or PLL
outputs.
Figure 4–9. GCLK Control Block for Stratix V Devices
Notes to
(1) When the device is in user mode, you can dynamically control the clock select signals through internal logic.
(2) When the device is in user mode, you can only set the clock select signals through a configuration file (SRAM object
You can set the input clock sources and the clkena signals for the GCLK and RCLK
network multiplexers through the Quartus II software using the ALTCLKCTRL
megafunction.
Clock source selection (dynamic selection available only for GCLKs)
Global clock multiplexing
Clock power down (static or dynamic clock enable or disable available only for
GCLKs and RCLKs)
file [.sof] or programmer object file [.pof]); they cannot be dynamically controlled.
4–9,
Figure
Figure
4–9:
4–10, and
CLKSELECT[1..0]
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
Outputs
(1)
Figure 4–11
2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
2
show the GCLK, RCLK, and PCLK control
Devices.
CLKp
Pins
2
Enable/
Disable
GCLK
CLKn
Pin
Static Clock
Select (2)
Internal
Internal
Logic
Logic
PLL Connectivity
4–13