NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 9

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
5.3
5.4
5.5
5.6
DMA Operation (D31:F0) .................................................................................. 103
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
LPC DMA ........................................................................................................ 106
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
8254 Timers (D31:F0) ..................................................................................... 110
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 113
5.6.1
5.6.2
5.6.3
5.6.4
®
6300ESB ICH
5.2.1.5
5.2.1.6
5.2.1.7
5.2.1.8
5.2.1.9
5.2.1.10 LPC Power Management........................................................... 102
5.2.1.11 Configuration and Intel
5.3.2.1
5.3.2.2
5.3.4.1
5.3.6.1
5.3.6.2
5.3.6.3
5.5.5.1
5.5.5.2
5.5.5.3
5.6.1.1
5.6.1.2
5.6.1.3
5.6.2.1
5.6.2.2
5.6.2.3
5.6.2.4
5.6.4.1
5.6.4.2
5.6.4.3
5.6.4.4
5.6.4.5
5.6.4.6
5.6.4.7
5.6.4.8
DMA Overview ..................................................................................... 103
Channel Priority ................................................................................... 104
Address Compatibility Mode ................................................................... 104
Summary of DMA Transfer Sizes ............................................................ 105
Autoinitialize........................................................................................ 105
Software Commands............................................................................. 106
Asserting DMA Requests........................................................................ 106
Abandoning DMA Requests .................................................................... 107
General Flow of DMA Transfers............................................................... 108
Terminal Count (TC) ............................................................................. 108
Verify Mode ......................................................................................... 108
DMA Request Deassertion...................................................................... 108
SYNC Field/LDRQ# Rules ....................................................................... 109
Counter 0, System Timer ...................................................................... 110
Counter 1, Refresh Request Signal.......................................................... 110
Counter 2, Speaker Tone....................................................................... 110
Timer Programming .............................................................................. 110
Reading from the Interval Timer............................................................. 111
Interrupt Handling ................................................................................ 114
Initialization Command Words (ICWx) ..................................................... 115
Operation Command Words (OCW) ......................................................... 116
Modes of Operation .............................................................................. 117
SYNC Time-Out ...................................................................... 100
SYNC Error Indication .............................................................. 100
LFRAME# Usage ..................................................................... 101
I/O Cycles.............................................................................. 102
Bus Master Cycles ................................................................... 102
Fixed Priority .......................................................................... 104
Rotating Priority ..................................................................... 104
Address Shifting When Programmed for 16-Bit I/O Count by Words 105
Clear Byte Pointer Flip-Flop ...................................................... 106
DMA Master Clear ................................................................... 106
Clear Mask Register ................................................................ 106
Simple Read........................................................................... 112
Counter Latch Command.......................................................... 112
Read Back Command .............................................................. 113
Generating Interrupts.............................................................. 114
Acknowledging Interrupts ........................................................ 115
Hardware/Software Interrupt Sequence ..................................... 115
ICW1 .................................................................................... 116
ICW2 .................................................................................... 116
ICW3 .................................................................................... 116
ICW4 .................................................................................... 116
Fully Nested Mode................................................................... 117
Special Fully-Nested Mode........................................................ 117
Automatic Rotation Mode (Equal Priority Devices)........................ 117
Specific Rotation Mode (Specific Priority).................................... 117
Poll Mode............................................................................... 118
Cascade Mode ........................................................................ 118
Edge and Level Triggered Mode ................................................ 118
End of Interrupt Operations...................................................... 118
®
6300ESB ICH Implications .................... 102
Intel
®
6300ESB I/O Controller Hub
DS
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