NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 687

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.7.7.3 Target Termination Received by the Intel
18.7.7.4 Target Termination Initiated by the Intel
18.7.8
18.7.9
November 2007
Order Number: 300641-004US
Note: When the Intel
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6300ESB ICH
abort is the expected termination for the special cycle on the target bus. In this case,
the master abort received bit is not set, and the Type 1 con-figuration transaction is
disconnected after the first data phase.
When the Intel
re-initiates the transfer with the remaining length. When the Intel
receives a target abort, and the cycle requires completion on the Hub Interface, the
Intel
completion status.
The Intel
transactions when any of the following conditions are met:
The Intel
met:
The Intel
or target aborted on the Hub Interface.
LOCK Cycles
A lock is established when a memory read from the Hub Interface that targets PCI with
the lock bit set, and at least one byte enable active, is responded to with a TRDY# by a
PCI target. The Intel
enables are asserted on the initial locked read request. The bus is unlocked when the
Unlock Special Cycle is sent on the Hub Interface.
When the bus is locked, the cycle is retried when a memory cycle originates on PCI that
is outside the range of the memory windows. No I/O cycles that are destined across the
bridge are accepted, whether the bus is locked or not, and then master abort.
Once the bus is locked, any Hub Interface cycle to PCI is driven with the LOCK# pin,
even when that particular cycle is not locked.
Error Handling
The Intel
on the PCI interfaces. Parity errors must always be reported to some system level
software, typically the device driver or the OS. This section describes how a standard
PCI bridge handles these errors. For enhanced error detection, see the RAS section
located section.
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A new transaction for delayed transaction queue.
The request has already been queued, but has not completed on the Hub Interface.
The delayed transaction queue is full, and the transaction cannot be queued.
The Intel
The Intel
When the memory address is non-linear
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— A LOCK transaction has been established from the Hub Interface to PCI.
6300ESB ICH returns the target abort code to the Hub Interface as the
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6300ESB ICH disconnects an initiator when one of the following conditions is
6300ESB ICH returns a target retry to an initiator for memory read
6300ESB ICH returns a target abort to PCI when the cycle master aborted
6300ESB ICH checks and generates parity on the Hub Interface and parity
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6300ESB ICH cannot accept any more write data
6300ESB ICH has no more read data to deliver
6300ESB ICH receives a retry or disconnect response from a target, it
6300ESB ICH performs a Type 1 to special cycle translation, a master
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6300ESB ICH does not support a split-lock request with no byte
Intel
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6300ESB ICH
6300ESB ICH
6300ESB I/O Controller Hub
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6300ESB ICH
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DS